The present invention relates to a clock generator used in a microprocessor or the like and, more particularly, to a clock generator which controls the generation of clock signals in accordance with an external control signal.
FIG. 1 shows the configuration of the conventional clock generator used in a microprocessor. This clock generator comprises an oscillator 1, a frequency divider 2, and a synchronizing control circuit 3. The oscillator 1 oscillates at a predetermined period in correspondence with the natural frequency of a quartz vibrator 4. The frequency divider 2 divides an oscillation output signal OSC from the oscillator 1, thereby generating a clock signal CLK which controls a microprocessor. The synchronizing control circuit 3 synchronizes the clock signal CLK with an external synchronizing signal SYN which is supplied to an external synchronizing control terminal 5.
When the supply of the clock signal CLK to a CMOS microprocessor is stopped so as to set the CMOS microprocessor in the standby mode to reduce its power consumption by utilizing a conventional clock generator of this type, the cycle of the clock signal CLK generated immediately beforehand cannot be properly completed depending on the timing of the external synchronizing signal SYN, as shown in the timing chart of FIG. 2. In other words, during a period T of one cycle of the clock signal CLK, a period of "0" level must be (2/3)T and a period of "1" level must be (1/3)T. However, when the external synchronizing signal SYN used as a clock stop control signal goes to "1" level with the timing shown in FIG. 2, the clock signal CLK is also at "1" level at this time, thereby stopping generation of the clock signal CLK. In this case, in a cycle immediately before stopping the clock signal CLK, a period TO during which the clock signal is at the "0" level becomes shorter than (2/3)T, and a duty cycle of the clock signal CLK is thereby disturbed. This can cause the microprocessor which is controlled by the clock signal CLK to malfunction. The reason will be described hereinafter.
A microprocessor generally forms, e.g., two phase clock signals .phi.1 and .phi.2 as shown in FIG. 3 by using a clock signal supplied from a clock generator. The microprocessor controls various operations by using the two phase clock signals .phi.1 and .phi.2. For example, as shown in FIG. 4, an internal circuit of the microprocessor comprises an input register 11, a circuit block 12 having a single function, and an output register 13. In this circuit, when one clock signal .phi.1 is at "1" level, input data or an input signal is written in the input register 11, and when the signal .phi.1 is at "0" level, this writing operation is stopped. When the other signal .phi.2 is at "1" level, a calculation or determination of a control signal by the circuit block 12 is performed in accordance with the data or signal written in the input register 11. In addition, during this period, output data or a signal from the circuit block 12 is supplied to the output register 13, thereby ensuring a high-speed and precise operation.
However, as shown in FIG. 2, when the clock signal CLK is stopped at an incorrect timing of the two phase clock signals .phi.1 and .phi.2 which are formed in the microprocessor from the clock signal CLK, the signal .phi.2 (or .phi.1) has a considerably shorter pulse width than normal, as shown in the timing chart of FIG. 5. Therefore, the predetermined operation of the microprocessor cannot be provided, thereby causing a malfunction of the microprocessor.